Different reasons motivate chip developers to use certain initialization mechanisms (i.e., asynchronous reset or set, or synchronous reset or set) for the flip flops in circuit designs. The reasons vary from easing simulation work to hard criteria for parts of the circuit to start in defined states after power up in the system. In some cases, legacy code from other designs is reused where initialization structures are already in the design.
In most designs, a particular initialization strategy is determined for implementation across an entire chip. After splitting the work between different developers and bringing the pieces back together at the end, no further checks are performed to determine whether the particular initialization scheme was implemented as planned in all parts of the design. In particular, no optimization of the initialization circuit is performed. The above approach happens more frequently in cases where legacy code is used from earlier designs.
Because of a growing number of flip flops in high complex multimillion gates designs, a tremendous overhead is commonly introduced by (i) choosing such overall schemes for initialization and (ii) poor optimization. The overhead is caused by different effects:
A) Flip flops that are used to implement an asynchronous reset commonly have a larger size than flip flops without reset. In cases where logic gates are used to implement the initialization circuitry, the gate count due to the asynchronous reset structures is larger than without the asynchronous reset structures.
B) Many extra cells are inserted and built into a tree, such as a reset net or similar structure, to reach all endpoints relevant for the initialization.
C) Because of a high fanout nature, the initialization nets often become a limiting factor for timing closure. As such, even more gates are used to parallelize logic to close the timing.